LPOSCEN=DISABLED, WAKEPAD_DISABLE=ENABLED, WAKEUPHYS=DISABLED, LPOSCDPDEN=DISABLED
Deep power-down control register
| WAKEUPHYS | WAKEUP pin hysteresis enable 0 (DISABLED): Disabled. Hysteresis for WAKEUP pin disabled. 1 (ENABLED): Enabled. Hysteresis for WAKEUP pin enabled. |
| WAKEPAD_DISABLE | WAKEUP pin disable. Setting this bit disables the wake-up pin, so it can be used for other purposes. Never set this bit if you intend to use a pin to wake up the part from Deep power-down mode. You can only disable the wake-up pin if the self wake-up timer is enabled and configured. Setting this bit is not necessary if Deep power-down mode is not used. 0 (ENABLED): Enabled. The wake-up function is enabled on pin PIO0_4. 1 (DISABLED): Disabled. Setting this bit disables the wake-up function on pin PIO0_4. |
| LPOSCEN | Enable the low-power oscillator for use with the 10 kHz self wake-up timer clock. You must set this bit if the CLKSEL bit in the self wake-up timer CTRL bit is set. Do not enable the low-power oscillator if the self wake-up timer is clocked by the divided IRC. 0 (DISABLED): Disabled. 1 (ENABLED): Enabled. |
| LPOSCDPDEN | Enable the low-power oscillator in Deep power-down mode. Setting this bit causes the low-power oscillator to remain running during Deep power-down mode provided that bit 2 in this register is set as well. You must set this bit for the self wake-up timer to be able to wake up the part from Deep power-down mode. Do not set this bit unless you use the self wake-up timer to wake up from Deep power-down mode. 0 (DISABLED): Disabled. 1 (ENABLED): Enabled. |
| RESERVED | Data retained during Deep power-down mode. |